9
11.Instruction description
11.1Outline
To overcome the speed difference between the internal clock of KS0066U and the MPU clock, KS0066U
performs internal operations by storing control in formations to IR or DR. The internal operation is determined
according to the signal from MPU, composed of read/write and data bus (Refer to Table7).
Instructions can be divided largely into four groups:
1) KS0066U function set instructions (set display methods, set data length, etc.)
2) Address set instructions to internal RAM
3) Data transfer instructions with internal RAM
4) Others
The address of the internal RAM is automatically increased or decreased by 1.
Note: during internal operation, busy flag (DB7) is read “High”.
Busy flag check must be preceded by the next instruction.
11.2 Instruction Table
Instruction code
Instruction
RS
R/W
DB7
DB6
DB
5
DB4
DB3
DB2
DB
1
DB0
Description
Execution
time (fosc=
270 KHZ
Clear
Display
0000000001DDRAM address to “00H” from
Write “20H” to DDRA and set
AC
1.53ms
Return
Home
000000001-Its original position if shifted.
Set DDRAM address to “00H”
From AC and return cursor to
The contents of DDRAM are
not changed.
1.53ms
Entry mode
Set
00000001I/DSHAssign cursor moving directionAnd blinking of entire display
39us
Display ON/
OFF control
0000001DCBBlinking of cursor (B) on/off
Set display (D), cursor (C), and
Control bit.
Cursor or
Display shift
000001S/CR/L--Shift control bit, and theDirection, without changing of
Set cursor moving and display
DDRAM data.
39us
Function
set
00001DLNF- -Bit/4-bit), numbers of display
Set interface data length (DL:
8-
Line (N: =2-line/1-line) and,
Display font type (F: 5x11/5x8)
39us
Set
CGRAM
Address
0001AC5AC4AC3AC2AC1AC0addressCounter.
Set CGRAM address in
39us
Set
DDRAM
Address
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
address
Counter.
Set DDRAM address in
39us
Read busy
Flag and
Address
0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
By reading BF. The contents of
Whether during internal
Operation or not can be known
Address counter can also be
read.
0us
Write data
to
Address
1 0 D7 D6 D5 D4 D3 D2 D1 D0
Write data into internal RAM
(DDRAM/CGRAM).
43us
Read data
From RAM
1 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data from internal RAM
(DDRAM/CGRAM).
43us
NOTE:
When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2fosc is
necessary for executing the next instruction by the falling edge of the “E” signal after the busy flag (DB7) goes
to “Low”.
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